In certain applications, including portable applications employing wireless handsets, circuitry utilized with such applications (e.g., input/output (IO) buffers, etc.) may be configured such that at least a portion of the circuitry runs off a battery supply while the rest of the circuitry runs off a separate power supply. Moreover, the battery supply may be required to operate at multiple voltage levels, such as, for example, 3.3 volts and 1.8 volts, with each voltage level having a specified tolerance (e.g., typically about ±10%) associated therewith. Such circuitry must generally meet predetermined design specifications at all operating voltages. In order to accomplish this, a voltage level detector is often used to identify which battery voltage level is being supplied to the circuit and to adjust the circuitry accordingly to meet the design specifications at the identified operating voltage.
One known technique for detecting the voltage level supplied to a circuit is shown in FIG. 1. A battery voltage VBAT is applied to the gate terminals (G) of a p-type metal-oxide-semiconductor (PMOS) transistor MP1 and an n-type MOS (NMOS) transistor MN1. A source terminal (S) of transistor MP1 is connected to the positive voltage supply VDD and a drain terminal (D) of MP1 is connected to the drain terminal (D) of transistor MN1. The source terminal (S) of MN1 is connected to the negative voltage supply VSS. Transistors MP1 and MN1 are thus configured as a standard inverter, with the gate terminals of MP1 and MN1 forming an input of the inverter and the drain terminals of MP1 and MN1 forming an output of the inverter at node N1.
The switching point of the inverter is typically skewed, for example, by adjusting the ratio of the channel widths and/or lengths of the two transistors MP1 and MN1, such that when the input voltage VBAT is 1.8 volts, it will be treated as a logical “0.” Subsequent stages of inverters (e.g., inverter 102) are sometimes added to generate an output that is a logical “1” when VBAT is 3.3 volts and a logical “0” otherwise.
A primary disadvantage with this conventional approach, however, is that the voltage level detector often fails when there is a voltage mismatch between the battery voltage VBAT and the positive voltage supply VDD. For example, if VDD is 10% higher than the 3.3 volt nominal operating voltage (i.e., 3.6 volts) and VBAT is 10% lower than the 3.3 volt nominal voltage (i.e., 3.0 volts), transistor MP1 may pull the output node N1 high due to sub-threshold operation of MP1 and also because transistor MN1 is often made weak in order to skew the switching point of the inverter. This will cause the output Z of the voltage level detection circuit to be a logical “0,” erroneously indicating that the lower voltage level of 1.8 volts is present when, in fact, the output should be a logical “1” indicating a 3.3 volt level of operation. Likewise, when VBAT is 1.8 volts, MP1 is turned on and MN1 is not completely turned off, thus dissipating substantial current in the circuit. In order to reduce this current and raise the switching point of the inverter, the channel length of transistor MN1 can be made substantially long compared to the channel length of transistor MP1. However, the long channel length transistor MN1 would occupy significant semiconductor area and is thus undesirable. Moreover, the high switching point of the inverter significantly reduces a noise margin of the circuit.
There exists a need, therefore, for an improved circuit for detecting multiple voltage levels that does not suffer from one or more of the problems exhibited by conventional voltage level detection circuitry.